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Created by Michael Steinel
over 8 years ago
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collection
grid
to split
row
column
to feed (fed)
pin
successive
to latch
proper
to await
i.e. (that is)
simultaneously
to place
to appear
delay
storage cells
strobe
split up
particular
availability
latency
measured
row/column address decoder
memory matrix
RAS (Row Address Strobe) Signal
row/column address latch
WE (Write Enable) signal
CAS (Column Address Strobe) signal
CAS Latency (CL)
nanosecond
clock cycle