NTEN 111 - Midterm 1 Study Guide

Question 1 of 83

1

Which of the following problems would NOT being identified during POST?

Select one of the following:

memory failure
bad monitor
bad video card
faulty CPU

Explanation

Question 2 of 83

1

In the figure below, Item D is the _______.

Select one of the following:

system board connections for IDE and floppy drives
DIMM slots
P1 power connection on the system board
PCI local bus slots

Explanation

Question 3 of 83

1

The correct order of the boot process is:

Select one of the following:

POST, User is able to execute application software, ROM BIO searches for and loads OS, OS configures the system and completes loading
POST, ROM BIO searches for and loads OS, OS configures the system and completes loading, User is able to execute application software
POST, OS configures the system and completes loading, User is able to execute application software
POST, User is able to execute application software, OS configures the system and completes loading, ROM BIO searches for and loads OS

Explanation

Question 4 of 83

1

What's the first thing the Startup BIOS looks for on a hard drive during boot up?

Select one of the following:

DOS Boot Record
Master Boot Record Correct
NT Boot Record
Piece of Pie

Explanation

Question 5 of 83

1

POST stands for:

Select one of the following:

partial operating system test
Power-off self test
Power-on self test
Pre-operational system test
None of the above

Explanation

Question 6 of 83

1

Which of the following is NOT a motherboard form factor:

Select one of the following:

ATX
Micro-PTX
LPX
BTX
AT

Explanation

Question 7 of 83

1

Which statement is NOT true about CMOS chips:

Select one of the following:

They maintain their settings long after you remove the CMOS battery
They generally hold between 64 bytes and 512 bytes of memory
They are sometimes referred to as NVRAM
They contain resource settings for plug-and-play devices in the ESCD
They contain the Real Time Clock that holds PC's time and date settings

Explanation

Question 8 of 83

1

How many of the following components are part of the CPU?

• ALU
• Real Time Clock
• branch predictor
• Registers
• Program Counter

Select one of the following:

1
2
3
4
5

Explanation

Question 9 of 83

1

Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?

Select one of the following:

Doubler and Tripler clocks
Derived System Clocks
Multiplier and Divider Clocks
Frequency Multiplexers

Explanation

Question 10 of 83

1

Which term is commonly used to reference the process of division and
multiplication of the system clock to achieve the desired frequency?

Select one of the following:

Doubler and Tripler clocks
Derived System Clocks
Multiplier and Divider clocks
Frequency Multiplexers

Explanation

Question 11 of 83

1

Secondary cache, also called ______ cache, may be located either in the
CPU cartridge or on the system board near the CPU.

Select one of the following:

L1
L2
L3
L4

Explanation

Question 12 of 83

1

How many of the following items are true regarding cache?
◦ Cache uses DRAM with is faster that SRAM (found in main memory)
◦ Cache is not always found in the CPU
◦ Cache is designed as temporary storage for the CPU
◦ The size of cache is matched to be equal to the amount of main memory in
the computer

Select one of the following:

0
1
2
3
4

Explanation

Question 13 of 83

1

Early Pentium CPUs are said to have multi-processing capabilities because they ____________

Select one of the following:

Can process data coming in while sending data out
Have the ability to exist with other processors
Use multiple registers
Contain two Arithmetic Logic Units Correct

Explanation

Question 14 of 83

1

Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.

Select one of the following:

L4
L3
L2
L1

Explanation

Question 15 of 83

1

Different speeds for computer components are achieved by using what is called ___________.

Select one of the following:

Frequency Multiplexers
Multiplier and Divider clocks
Derived System Clocks
Doubler and Tripler clocks

Explanation

Question 16 of 83

1

Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.

Select one of the following:

I/O Controller Hub
ISA bus
Graphics Memory Controller Hub
South Bridge

Explanation

Question 17 of 83

1

The amount of addressable memory is determined by the size of the address bus.

Select one of the following:

True
False

Explanation

Question 18 of 83

1

The Multiplier is the term used to describe the ________________

Select one of the following:

the ratio of the Backside Bus speed to the Memory Bus speed
the ratio of the Backside Bus speed to the CPU operating speed
the ratio of the CPU operating speed to the Front Side Bus speed
the ratio of the PCI bus speed to the Memory Bus speed

Explanation

Question 19 of 83

1

The front side bus connects the CPU to the ______.

Select one of the following:

coprocessor
L1 cache
system clock
memory bus

Explanation

Question 20 of 83

1

A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump

Select one of the following:

Control Unit
Branch Predictor
Hyper-Threading Technology
Cache

Explanation

Question 21 of 83

1

A unit that controls the operations of all components in the processor and executes conditional instructions

Select one of the following:

control unit
Instruction Register
Branch Predictor
ALU

Explanation

Question 22 of 83

1

Allows access to the hard disk drive, USB ports and other I/O devices

Select one of the following:

Cache
Program Counter
North Bridge
South Bridge

Explanation

Question 23 of 83

1

Allows access to the RAM and video card

Select one of the following:

North Bridge
South Bridge
West Bridge
East Bridge

Explanation

Question 24 of 83

1

A processor design where the circuitry for each stage of the pipeline is duplicated to allow multiple instructions to pass through in parallel

Select one of the following:

Cache
Arithmetic Logic Unit
Hyper-Threading Technology
Superscalar Architecture

Explanation

Question 25 of 83

1

An internal memory location that contrains the instruction that is to be executed.

Select one of the following:

Cache
Instruction Register
Branch Predictor
South Bridge

Explanation

Question 26 of 83

1

The part of the CPU that processes arithmetic and logical instructions

Select one of the following:

Floating Point Unit
Arithmetic Logic Unit
Multiplier Bus
Divisor Programming Unit

Explanation

Question 27 of 83

1

An internal memory location that contains the address of the next instruction to be executed

Select one of the following:

Counting Register
Address Bus Architecture
Address Memory Unit
Program Counter

Explanation

Question 28 of 83

1

Used as temporary storage for the CPU

Select one of the following:

RAM
ROM
Cache
Hard Disk Drive

Explanation

Question 29 of 83

1

The ___________ contains a group of secondary chips that relieves the CPU of processing traffic to and from all the buses and controllers on the system board.

Select one of the following:

DMA Controller
IRQ Controller
Chipset
Super I/O

Explanation

Question 30 of 83

1

Which three Buses connect to the GMCH in the Accelerated Hub Architecture Chipset design developed by Intel ? (Select three)

Select one or more of the following:

ISA
System
AGP
Memory
VESA-Local Bus
PCI

Explanation

Question 31 of 83

1

With 486 and higher CPUs, the cache controller is ________.

Select one of the following:

attached to the CMOS chip
not required, as the CPU itself controls the cache
housed on the system board
embedded in the CPU chip

Explanation

Question 32 of 83

1

Although different manufacturers may refer it with different proprietary names, the fast end of the Chipset Hub Architecture is still commonly referred to as the hub's ________.

Select one of the following:

Fast Bridge
ICH
North Bridge
South Bridge

Explanation

Question 33 of 83

1

Which of the following items relieves the CPU of processing traffic to
and from all the buses and controllers on the system board?

Select one of the following:

IRQ Controller
Chipset
DMA Controller
Super I/O

Explanation

Question 34 of 83

1

The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.

Select one of the following:

South Bridge
North Bridge
ICH
East Bridge
West Bridge

Explanation

Question 35 of 83

1

How many of the following buses connect to the GMCH in the
Accelerated Hub Architecture Chipset?
•PCI • System
• Memory • AGP
• ISA • VESA-Local Bus

Select one of the following:

1
2
3
4
5

Explanation

Question 36 of 83

1

Early IDE drives followed the IDE/ATA (Integrated Device Electronics AT Attachment) standard which used CHS mode translation and limited drive size to _____ Megabytes.

Select one of the following:

356
504
768
943

Explanation

Question 37 of 83

1

A SCSI chain must be terminated either by a passive, active or forced perfect terminator.

Select one of the following:

True
False

Explanation

Question 38 of 83

1

With IDE drives, the OS executes the remainder of the format process. This is known as a _____.
Select one:

Select one of the following:

low level format
high-level format
partition
part

Explanation

Question 39 of 83

1

Beginning with IDE technology, the number of sectors per track varied depending on the location of the track.

Select one of the following:

True
False

Explanation

Question 40 of 83

1

Which SCSI ID would usually be used for Hard Drives?

Select one of the following:

0
2
4
7

Explanation

Question 41 of 83

1

In a process called _____, track and sector markings are written on the hard drive at the factory.

Select one of the following:

high-level formatting
low level formatting
partitioning
parking

Explanation

Question 42 of 83

1

IDE drives use a _____-pin cable.

Select one of the following:

34
40
50
68

Explanation

Question 43 of 83

1

LBA, or logical block addressing, is the most suitable translation mode for large capacity drives in use today.

Select one of the following:

True
False

Explanation

Question 44 of 83

1

What newer technology is being used to replace the 40 pin ribbon cables that have been used in the past for Hard Drives?

Select one of the following:

Parallel ATA
Serial ATA
Synchronous ATA
Single Mode ATA

Explanation

Question 45 of 83

1

Low level formatting of an IDE drive could permanently destroy the drive data and render the drive unusable.

Select one of the following:

True
False

Explanation

Question 46 of 83

1

Zone Bit Recording means ___________________

Select one of the following:

the number of sectors/track vary depending on the location of the track.
the tracks are arranged so the same number of sectors are used for all tracks.
each bit is recorded one zone at a time
a type of logical method of addressing larger capacity drives

Explanation

Question 47 of 83

1

Serial ports transmit data one byte at a time.

Select one of the following:

True
False

Explanation

Question 48 of 83

1

Which of the following is NOT a type of parallel port?

Select one of the following:

SPP
EPP
ECP
EDP

Explanation

Question 49 of 83

1

Parallel ports transmit data in parallel, _____ bit(s) at a time.

Select one of the following:

1
2
4
8

Explanation

Question 50 of 83

1

When the hard drive BIOS communicates with the system BIOS in a translation method unrelated to cylinders, heads and sectors, _______ mode is being used.

Select one of the following:

Normal
LBA
CHS
ECHS

Explanation

Question 51 of 83

1

Which of the following is true about SCSI vs EIDE?

Select one of the following:

EIDE is harder to set up than SCSI
SCSI is faster and more expensive
EIDE is faster and more expensive
SCSI is more popular than EIDE

Explanation

Question 52 of 83

1

The IDE/ATA standard for a hard drive set the maximum values for Cylinders/Heads/Sectors to be 65,536/16/256. Based on this CHS calculation, what will be the maximum hard drive capacity allowed?

Select one of the following:

504 MB
7.88 Gbits
128 GB
7.88 GB

Explanation

Question 53 of 83

1

In IDE and SCSI drives, a(n) _____ is mounted on a circuit board on the drive housing and is an integral part of the drive.

Select one of the following:

adapter
ROM bios
CMOS chip
controller

Explanation

Question 54 of 83

1

The number of sides or surfaces of hard drive platters contained in a hard disk is also referred to as the number of _____.

Select one of the following:

actuators
heads
platters
spindles

Explanation

Question 55 of 83

1

A null-modem cable can be used to directly connect two ____ devices.

Select one of the following:

DTE
DCE
DCA
DMA

Explanation

Question 56 of 83

1

Which statement is NOT true about CMOS chips:

Select one of the following:

They maintain their settings long after you remove the
CMOS battery
They generally hold between 64 bytes and 512 bytes of
memory
They are sometimes referred to as NVRAM
They contain resource settings for plug-and-play devices in
the ESCD (Extended System Configuration Data) area
The contain the Real Time Clock that holds the PC’s time
and date settings

Explanation

Question 57 of 83

1

The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.

Select one of the following:

South Bridge
North Bridge
ICH
East Bridge
West Bridge

Explanation

Question 58 of 83

1

Parallel ports are only able to transmit data in one direction at any given
time.

Select one of the following:

True
False

Explanation

Question 59 of 83

1

Synchronous memory requires an external clock signal while
Asynchronous does not.

Select one of the following:

True
False

Explanation

Question 60 of 83

1

How many of the following statements are true?
◦ DRAM is always faster that SRAM
◦ SRAM is lower cost that DRAM
◦ Both DRAM and SRAM are available in synchronous and asynchronous forms
◦ Both SRAM and DRAM retains values when the power is off

Select one of the following:

0
1
2
3
4

Explanation

Question 61 of 83

1

How many of the following statements are true?
◦ DRAM does not require refreshing to hold data
◦ SRAM allows for faster data access that DRAM
◦ SRAM costs more than DRAM per byte
◦ SRAM and DRAM memory cells are the same physical size per byte

Select one of the following:

0
1
2
3
4

Explanation

Question 62 of 83

1

How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors

Select one of the following:

0
1
2
3
4

Explanation

Question 63 of 83

1

How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors

Select one of the following:

Even
Odd

Explanation

Question 64 of 83

1

Which BUS version is set to replace AGP?

Select one of the following:

PCIe
ISA
Infiniband
PCI-X

Explanation

Question 65 of 83

1

With parity memory, the 8th bit is used to store parity for the bytes and as a result can only store a 7-bit value.

Select one of the following:

True
False

Explanation

Question 66 of 83

1

Synchronous SRAM is more expensive and about 30% slower than asynchronous SRAM.

Select one of the following:

True
False

Explanation

Question 67 of 83

1

What kind of Parity checking is being used if the following byte of data and it's parity bit are correct:
Value: 1011 0111 Parity Bit: 1

Select one of the following:

even
equal
odd
balanced

Explanation

Question 68 of 83

1

Complete the following statement: _ RAM holds data for a very short period of time and needs to be constantly refreshed, whereas _ RAM, because of its construction, holds data until the power is turned off.

Select one of the following:

PRAM, DRAM
SRAM, DRAM
DRAM, SRAM
SRAM, PRAM

Explanation

Question 69 of 83

1

What is the name given to the automatic detection of the Manufacturer BIOS timing settings for a specific memory module via an EEPROM chip?

Select one of the following:

Ram Timing Detect
Auto-Timing Detect
Serial Presence Detect
Memory Alert

Explanation

Question 70 of 83

1

Generally speaking (and excluding Flash memory), RAM can be divided into two major categories, and those categories are static and dynamic.

Select one of the following:

True
False

Explanation

Question 71 of 83

1

You have a system board that accepts DDR266 RAM (ie. twice clock speed) but whose actual clock speed for the memory bus is 133MHz. You are using the AMD Athlon chip (Comparable to PIII). What is the approximate possible throughput of the memory bus with this combination in gigabytes per second?

Select one of the following:

1.6GB/s
2.1GB/s
3.2GB/s
1.06GB/s

Explanation

Question 72 of 83

1

One error-checking procedure for memory, whereby either every byte has an even number of ones or every byte has an odd number of ones is known as _____.

Select one of the following:

checksum
bit parity
ESCD
PRAM

Explanation

Question 73 of 83

1

What type of bus is displayed in the figure below

Select one of the following:

16-bit ISA
VESA
8-bit ISA
PCI

Explanation

Question 74 of 83

1

The 16-bit ISA bus contains an extra IRQ lines and DMA channels above and beyond what is available for the 8 bit ISA Bus.
(HINT: Remember DMA Channel 4 is used for the controller and not available to the bus)

Select one of the following:

6,3
3,6
5,3
5,4

Explanation

Question 75 of 83

1

Which of the following is a list of expansion bus types ?

Select one of the following:

MCA, PCI, Memory
ISA, EISA
ISA, PCD, AGD
PCI, DIMM, SIMM

Explanation

Question 76 of 83

1

The ______ ISA bus was so named because it had only an eight-bit data path.

Select one of the following:

4-bit
8-bit
16-bit
32-bit

Explanation

Question 77 of 83

1

ECC may be present on DIMM module, and correct single bit errors when possible.

Select one of the following:

True
False

Explanation

Question 78 of 83

1

DRAM SIMMs rapidly lose their data and must be refreshed every 3.86 milliseconds.

Select one of the following:

True
False

Explanation

Question 79 of 83

1

Using even parity, the computer makes the parity bit a 1 or 0 to make the number of ones in a byte _____.

Select one of the following:

even
equal
odd
balanced

Explanation

Question 80 of 83

1

All data stored in _____ is lost when the power is turned off.

Select one of the following:

PRAM
RAM
ROM
CMOS

Explanation

Question 81 of 83

1

On AGP 8x bus, the maximum throughput is ___________ (The current specs on an AGP bus are 32 bit Data Path and a 66 MHz clock)

Select one of the following:

2.1 GB/s
1.6 GB/s
500 MB/s
3.2 GB/s

Explanation

Question 82 of 83

1

	Created by j.salvino almost 9 years ago

Preperation for NTEN 111 at Okanagan College (2015, Berg)

NTEN 111 - Midterm 1 Study Guide

Question 1 of 83

Which of the following problems would NOT being identified during POST?

Select one of the following:

Explanation

Question 2 of 83

In the figure below, Item D is the _______.

Select one of the following:

Explanation

Question 3 of 83

The correct order of the boot process is:

Select one of the following:

Explanation

Question 4 of 83

What's the first thing the Startup BIOS looks for on a hard drive during boot up?

Select one of the following:

Explanation

Question 5 of 83

POST stands for:

Select one of the following:

Explanation

Question 6 of 83

Which of the following is NOT a motherboard form factor:

Select one of the following:

Explanation

Question 7 of 83

Which statement is NOT true about CMOS chips:

Select one of the following:

Explanation

Question 8 of 83

How many of the following components are part of the CPU? • ALU • Real Time Clock • branch predictor • Registers • Program Counter

Select one of the following:

Explanation

Question 9 of 83

Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?

Select one of the following:

Explanation

Question 10 of 83

Which term is commonly used to reference the process of division and multiplication of the system clock to achieve the desired frequency?

Select one of the following:

Explanation

Question 11 of 83

Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.

Select one of the following:

Explanation

Question 12 of 83

Select one of the following:

Explanation

Question 13 of 83

Early Pentium CPUs are said to have multi-processing capabilities because they ____________

Select one of the following:

Explanation

Question 14 of 83

Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.

Select one of the following:

Explanation

Question 15 of 83

Different speeds for computer components are achieved by using what is called ___________.

Select one of the following:

Explanation

Question 16 of 83

Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.

Select one of the following:

Explanation

Question 17 of 83

The amount of addressable memory is determined by the size of the address bus.

Select one of the following:

Explanation

Question 18 of 83

The Multiplier is the term used to describe the ________________

Select one of the following:

Explanation

Question 19 of 83

The front side bus connects the CPU to the ______.

Select one of the following:

Explanation

Question 20 of 83

A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump

Select one of the following:

How many of the following components are part of the CPU?

• ALU
• Real Time Clock
• branch predictor
• Registers
• Program Counter

Which term is commonly used to reference the process of division and
multiplication of the system clock to achieve the desired frequency?

Secondary cache, also called ______ cache, may be located either in the
CPU cartridge or on the system board near the CPU.

Which of the following items relieves the CPU of processing traffic to
and from all the buses and controllers on the system board?

The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.

How many of the following buses connect to the GMCH in the
Accelerated Hub Architecture Chipset?
•PCI • System
• Memory • AGP
• ISA • VESA-Local Bus